1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems including a register file supporting different sizes of source register such that aliasing between registers can occur and further including scheduling circuitry that detects data dependency hazards between micro-operations to be issued.
2. Description of the Prior Art
It is known to provide data processing systems with register files that may be addressed using registers of different sizes. For example, the register file of the ARM VFP (vector floating point) architecture provides a single register file shared by single-precision and double-precision instructions such that two single precision registers can map to one double precision register. This can create potential data dependencies (hazards) between single-precision register producers and double-precision register consumers. These dependencies can be managed relatively straight forwardly in an in-order processor but become harder to efficiently manage in an out-of-order processor, particularly one employing register renaming.
It is known from “Register Renaming For x86 Superscalar Design” by Chang-Chung Liu et al (IEEE 1996 International Conference On Parallel And Distributed Systems, Proceedings, page 336-343) to provide a mechanism whereby multiple rename tags at the smallest granularity with which the register file can be addressed are utilized for all instructions. In this way, any data dependency between one or more source registers and a larger destination register may be tracked and managed. Such an approach suffers from a disadvantage that it significantly increases the amount of state data associated with tracking data sources which must be managed within the processor and passed along the pipeline. Liu also discloses a technique whereby source registers are tracked until only one remains outstanding for an instruction at which point the instruction may be controlled based upon the availability of this one outstanding source register.
An alternative approach may be to detect a data hazard due to aliasing within the register file and when such hazards are detected for an instruction to be issued, then stall that instruction until the potential hazard has been removed. This approach is relatively simple to implement, but has a potentially significant adverse performance impact. While it might be considered that it would be rare to encounter a sequence of micro-operations in which a source register for a second (following) micro-operation depends on a destination register for a first (preceding micro-operation where these source and destination registers differ in size (since these two different sizes would typically indicate different, incompatible data types), however in practice it is found that such code sequences do occur within legitimate code (e.g. state saving and restore upon a context switch) and accordingly such a simple approach has too great an impact upon real life performance.